1. Field of the Invention
The invention relates to a data channel transmission system which data are channel-sequentially structured in frames and/or multiple frames.
2. Related Art
Such transmission systems are used, for example, for video conferencing which satisfies CCITT Recommendation H.261 and during which data are exchanged over an ISDN network. When data are exchanged between codecs over the ISDN network, a problem occurs which can be gathered from the following embodiments.
The bit rates for the video data of the codecs can be adjusted from 64 kbit/s to p*64 kbit/s, where p is an integer and satisfies the limitation 2.ltoreq.p.ltoreq.30. Since also acoustic signals are to be transmitted, no less than two ISDN base channels of 64 kbit/s each are necessary for satisfying the minimum requirements made on, for example, a videophone operation. However, since the channels in the ISDN network are separately automatically switched, the two sub-signals might arrive at the same receiver with considerable time differences. Delay differences of the order of up to one second may be considered realistic.
More specifically, the following processes take place when data of a video codec are transmitted over an ISDN network: The video coder first issues a serial data stream structured in accordance with Recommendation H.261. This data stream has a bit rate of p.times.64 kbit/s. A demultiplexer distributes this data stream over p channels and the respective data of each of the channels are simultaneously arranged in frames according to CCITT Recommendation H.221. Optionally, also acoustic data are arranged in the H.221 frames. In the time-division multiplex method the data of one of these channels are transmitted over the ISDN network, whilst at worst the data of one of each of these channels reach the receiver through another path. A multiplexer on the receiver side thus has for its object to equalize the delay differences of the channel data and arrange them in such a way that a reconstruction to the original serial data stream is possible. Circuit arrangements by which the delay differences of two B channels are equalized are known (the H.221-Muldex Integrated Circuit. CSELT, Mar. 1, 1990). Attempts at equalizing the delay differences by signal processors have shown that already with two channels the computing performance of conventional processors is exhausted.